In recent years, unconventional nonvolatile memory (NVM) devices, such as ferroelectric random access memory (FRAM) devices, phase-change random access memory (PRAM) devices, and resistive random access memory (RRAM) devices, have emerged. In particular, RRAM devices, which exhibit a switching behavior between a high resistance state and a low resistance state, have various advantages over conventional NVM devices. Such advantages include, for example, compatible fabrication steps with current complementary-metal-oxide-semiconductor (CMOS) technologies, low-cost fabrication, a compact structure, flexible scalability, fast switching, high integration density, etc.
As integrated circuits (ICs), which include such RRAM devices, become more powerful, it is desirable to maximize the number of the RRAM devices in the IC accordingly. Generally, an RRAM device includes a top electrode (e.g., an anode) and a bottom electrode (e.g., a cathode) with a variable resistive material layer interposed therebetween. In particular, an active area of the variable resistive material layer typically extends in parallel with the top and bottom electrodes, respectively. Forming the RRAM device in such a stack configuration that each layer can only extend two-dimensionally may encounter a trade-off between maximizing the number of the RRAM devices in the IC and maintaining optimal performance of the RRAM device. For example, the number of the RRAM devices is typically proportional to a number of the active areas of the variable resistive material layers. As such, within a given area of the IC, when the number of the RRAM devices is increased, the active area of each of the RRAM device shrinks, which may disadvantageously impact respective performance of each of the RRAM devices due to weaker signal coupling between respective top and bottom electrodes.
Thus, existing RRAM devices and methods to make the same are not entirely satisfactory.